1. Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically, to a method for fabricating a semiconductor device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for fabricating a device isolation film and a gate line after formation of a doped polysilicon layer on a semiconductor substrate.
2. Description of the Related Art
FIGS. 1a through 1d are cross-sectional views illustrating a related art method for fabricating a semiconductor device. Referring to FIG. 1a, a device isolation film 20 defining an active region is formed on a semiconductor substrate. Referring to FIG. 1b, a stacked structure of a gate oxide film 30, a gate polysilicon layer 40, a gate metal layer 50 and a hard mask layer 60 is then formed on the semiconductor substrate 10 and the device isolation film 20.
A photoresist film (not shown) is deposited on the hard mask layer 60. The photoresist film (not shown) is then exposed and developed to form a photoresist film pattern (not shown) defining a gate region. Thereafter, the stacked structure is etched using the photoresist film pattern as an etching mask to form gate structures 65 that each include a gate oxide film pattern 30a, a gate polysilicon layer pattern 40a, a gate metal layer pattern 50a and a hard mask layer pattern 60a, as shown in FIG. 1c. Thereafter, the photoresist film pattern is removed.
Referring to FIG. 1d, the semiconductor substrate 10 is subjected to an ion implantation process using the gate 65 structures as a mask. Gate spacers 70 are then formed on sidewalls of the gate structures 65. Next, a polysilicon layer is formed to fill up the openings between the gate structures 65 having the gate spacers 70. The polysilicon layer is then subjected to a chemical-mechanical polishing (CMP) process to form polysilicon plugs 80 for contacting to regions of the semiconductor substrate 10.
In accordance with the above-described conventional method, the polysilicon plugs are formed after the device isolation film and the gate line are formed. Accordingly, it is difficult to form the polysilicon plugs, which fill the openings between the gate structures, as the openings are decreased in size when the integration density is increased. Moreover, during an etching process for forming the openings between the gate structures, a surface of the semiconductor substrate may be damaged or the semiconductor substrate may not be completely exposed.